In memory integrated circuits, sense amplifiers detect and determine the data content of a selected memory cell. In electrically erasable programmable read only memories (“EEPROM”) and Flash memories, the sense amplifier serves two functions. First, the sense amplifier charges the bit line to a clamped value. Second, the sense amplifier senses the current flowing into the bitline due to the memory cell state. Both the reliability, in terms of endurance and retention, and the performance of the memory, in terms of access time and power consumption, are dependent on the design of the sense amplifier.
Usually, integrated sense amplifier structures are based on a differential amplifier comparing the current coming from the selected memory cell to the current of a reference cell. Reference cells can be implemented in a number of ways, including arrays of reference cells. A reference current may also be supplied by a “dummy” bit line equivalent to a standard bit line. When reference cells are employed, they are programmed once during the testing of the memory, increasing testing time.
In order to ensure good functionality of the sense, the ratio Icell/Iref, where Icell is the memory cell current and Iref is the reference current, must be maintained high enough to take account of process fluctuations in the memory and references cells as well as the impact of memory cycling. It has been shown that the speed, performance, and reliability of standard differential amplifier sense amplifiers are highly reduced for supply voltages less than 2 V.
In general, previous attempts to design sense amplifiers that do not employ reference cells are fully asynchronous and are not very suitable at a low supply voltage (i.e., VDD<1.2 V). Therefore, it would be desirable to have an improved sense amplifier design.